In this mode of operation, the timer functions as a one-shot (Figure 1). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. For More information: www.study2placement.blogspot.com
The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply.
Welcome to S2P Group.
VCC = 5V
TIME = 0.1 ms/DIV.
RA = 9.1kΩ
C = 0.01µF
During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to thereset terminal (pin 4). The output will then remain in the lowstate until a trigger pulse is again applied.When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering. Figure 3 is a nomograph for easy determination of R, C values for various time delays.
NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle.
0 comments:
Post a Comment